Optimized Reconfigurable MAC Processor Architecture

A network processor architecture with application-optimized reconfigurable processing paths (FlexPath NP)

Design Fpga Based Multi Rail Dc-dc Converter and Mac Architecture by Using Msp 430 Processor

This paper proposed Mixed signal processor (MSP) based digital controllers are specifically optimized. The proposed single multiply-accumulate (MAC) architecture has implemented using field programmable gate array (FPGA) and design multi converter. A detailed description of flexible single multiplier accumulator processor architecture is given and comparison is made with an existing solution wi...

Performance Analysis of a Reconfigurable Shared Memory Multiprocessor System for Embedded Applications

This paper presents a method to predict perform processor cores in a reconfigurable system for embedded applications. A multiprocessor framework is developed with the capability of reconfigurable processors in a shared memory system optimized for stream signal processing applications. The framework features a discrete time Markov based stochastic tool, which is used to analyze memory contention...

ACEcard: A High-Performance Architecture for Run-Time Reconfiguration

Recent FPGA architectures have shown an increased emphasis on run-time reconfiguration, or the ability to rapidly change the functionality of the FPGA to sequentially accommodate large processing tasks. In addition, partial reconfiguration allows for the reconfiguration of a portion of the FPGA while the remainder is running. These two features enable the use of reconfigurable computing in high...

A High-Performance Reconfigurable Elliptic Curve Processor for GF (2)

This work proposes a processor architecture for elliptic curves cryptosystems over fields GF (2). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bitparallel squarer, a digit-serial mu...